1. Field of the Invention
The present invention relates generally to signal measurement systems and, more particularly, to allocating hardware resources to perform a user-specified measurement in a logic analyzer.
2. Related Art
Analyzers and testers are commonly available to assist in the development, manufacturing and troubleshooting of complex digital electronic/software devices and integrated circuits having incorporated therein microprocessors, random-access memories (RAM), read-only memories (ROM), and other circuits. Such analyzers and testers, generally referred to herein as signal measurement systems, include, for example, logic analyzers, digital oscilloscopes, protocol analyzers, microprocessor emulators, bit error rate testers and network analyzers. Logic analyzers in particular have emerged for this purpose and are commercially available from a number of vendors such as Agilent Technologies, Inc., Tektronix, Inc., and others.
Logic analyzers are digital data acquisition instruments that allow a user to acquire and display digital signal data from a large number of logic signals such as those that travel over address, data and control lines of a device under test. A device under test may include a printed wiring board, printed circuit board, including microprocessors, memory circuits and other circuits and circuit components.
The logic signals are acquired from the device under test on hardwired lines referred to as data channels. The channels may be physically assembled into groups commonly referred to as pods. The received signals are sampled and digitized to form signal data. Digitizing typically includes comparing a voltage magnitude of each logic signal sample to a reference voltage threshold to determine the logic state of the signal. Sampling may occur at one of a number of selectable rates, depending on the frequency at which the sampled signals change logic states. The resultant signal data are stored, under the control of a sampling clock, in a signal data memory generally having a fixed size. The data are typically stored in a sequential manner such that consecutive signal samples are stored in consecutive memory locations. Due to the quantity of signal data, signal data memory is commonly implemented as a wrap-around buffer.
Selection of the portion of the signal data that is separately stored and subsequently presented on the display is determined by a user-defined trigger specification, referred to herein as a trigger sequence. A trigger sequence is functionally divided into one or more sequence levels to assist in the development and definition of complex trigger specifications. Each sequence level, in turn, includes one or more trigger to branches. Each trigger branch includes one or more trigger events and an occurrence specification together identifying the condition under which functions defined by an action list of the trigger branch are performed. A trigger event is defined as an occurrence of certain characteristics or properties of a signal, such as a rising or falling edge, a logic high or logic low signal state, etc. Events may also be defined based on internal resources, such internal timers, counters, etc. Typically, a branch condition specifies a number of events that occur simultaneously. The trigger branch condition is expressed by a Boolean expression referred to herein as a branch condition statement. Typically, the branch condition statement includes as one event an identification of the signal data that is to be captured.
Thus, a trigger sequence is comprised of one or more trigger sequence levels each including any number of trigger branches each of which includes a branch condition the occurrence of which causes the logic analyzer to execute the action defined in that trigger branch. Such execution results in the storage of signal data or further processing of a subsequent sequence level. Ultimately, execution of a trigger branch results in the storage of a predetermined quantity of signal data occurring before and after the portion of the signal that satisfied the specified trigger condition.
After the trigger specification is specified, the user can perform a measurement; that is, initiate acquisition of signal samples. When signal data capture is initiated, currently received signal data is compared to the specified trigger sequence. When the trigger sequence is satisfied, the signal data is captured in accordance with specified trigger control parameters. Subsequently, the signal data memory may be sequentially accessed and the captured signal data displayed.
Conventional logic analyzers present on a display device a measurement specification model that is nearly a direct representation of the analyzer""s internal hardware architecture to be programmed by the user. The user defines the trigger sequence by programming the hardware elements of the acquisition hardware through the displayed measurement specification model. The user constructs a trigger sequence by specifying which hardware resources shall participate in each term of the trigger sequence and how the resources are to be logically combined. This low-level hardware component configuration information is stored by the user interface and used by the analyzer software drivers to program the acquisition hardware.
This low-level, hardware component programming of the logic analyzer hardware resources prevents the efficient and accurate development of signal measurement specifications. The display of the underlying hardware architecture on the user interface is difficult for a user to understand and utilize. In addition, subsequent logic analyzer designs may implement a different hardware architecture to meet different speed and functionality design goals. Presenting a direct representation of the new architecture to the operator requires the design of a new measurement specification model for display on the user interface. Also, the user will thereafter be required to learn and understand the new measurement specification model. Furthermore, it may not be possible to use the measurement specifications made using one measurement specification model on a different type of logic analyzer due to differences in the underlying hardware architecture. These drawbacks only become more prohibitive to the productive use of the logic analyzers as they increase in complexity. Thus, as logic analyzers become more advanced, the number of qualified users decreases.
What is needed, therefore, is a system and method for facilitating the allocation of logic analyzer hardware resources.
The present invention is directed to systems and methodologies for use in signal measurement systems that acquire and store signal data in accordance with a trigger specification. In particular, the present invention is directed to a hardware resource allocator that is interposed between the signal acquisition hardware and graphical user interface on which a signal measurement specification model is presented to the user. The hardware resource allocator translates the measurement requirements specified by the user on the user interface to hardware configuration commands and data for allocation and control of the appropriate combination of hardware resources. Generally, the hardware resource allocator allocates and configures the requisite hardware resources and translates the measurement specification to hardware control data used by software drivers to program the signal acquisition hardware resources. Advantageously, the hardware resource allocator separates the architecture of the logic analyzer signal acquisition hardware from the measurement specification model presented on the user interface. As a result, the measurement specification model presented by the graphical user interface is not limited or otherwise dictated by the architecture of the signal acquisition hardware. In contrast to conventional systems subject to such limitations, the user interface may provide any measurement specification model to the user that is not a representation of or otherwise dictated by the underlying hardware architecture. This also frees the hardware architecture to be optimized for speed and efficiency without having to consider the adverse impact that an increasingly complex programming model may pose to the user. A further advantage of the invention is that the same measurement specification model can be used with logic analyzers that vary in the underlying signal acquisition hardware architecture. This allows the same software to be leveraged across multiple signal measurement platforms, saving considerable cost and time associated with converting or regenerating such measurement specification models. This also saves time and cost associated with user inefficiencies related to the use of different measurement specification models.
A number of aspects of the invention are summarized below, along with different embodiments of each of the summarized aspects. It should be understood that the embodiments are not necessarily inclusive or exclusive of each other and may be combined in any manner that is non-conflicting and otherwise possible, whether they be presented in association with a same or different aspect of the invention. It should also be understood that these summarized aspects of the invention are exemplary only and are considered to be non-limiting.
In one aspect of the invention a signal measurement system is disclosed. The signal measurement system includes a signal acquisition hardware module connected to a plurality of data channels over which logic signals travel and a user interface displaying a measurement specification model through which a user can specify a trigger sequence. The signal measurement system includes a hardware resource allocator that translates trigger branch condition statements of the trigger sequence to resource control data that allocates and controls portions of the signal acquisition hardware module to acquire and store signal data in accordance with the trigger sequence.
In one embodiment, the hardware resource allocator includes a translator that generates, for each trigger branch condition statement, resource control data that allocates and programs an event resource to implement each of the events in the trigger branch condition statement. The hardware resource allocator also includes a plurality of event combiners each programmable by the translator to evaluate a programmed Boolean combination of a programmed plurality of signals generated by the allocated event resources indicating whether the event occurred. Preferably, the plurality of event combiners are implemented as RAM look-up tables (LUTs) populated by the translator with 1""s and 0""s to implement a programmed Boolean combination of a plurality of programmed LUT inputs.
In certain embodiments, the hardware resource allocator also includes a measurement specification data structure, reflective of the measurement specification model, that stores the trigger sequence, and a resource control data structure that models an architecture of the acquisition hardware module and which stores the resource control data.
In embodiments in which the trigger branch condition statement is a complex Boolean expression, the event combiners are interconnected in a logically hierarchical arrangement that includes a plurality of pre-combiners and a post-combiner. The pre-combiners are connected to one or more of the programmed event resources to implement a Boolean combination of event result signals generated by the connected event resources. Such pre-combiners generate a signal representing the implemented Boolean combination of event resources. The post-combiner is connected to the plurality of pre-combiners to implement a Boolean combination of received pre-combiner result signals. The post-combiner generates a signal indicating whether the branch condition statement has been evaluated as true of false for a currently-received logic signal.
In another aspect of the invention a plurality of hardware modules for use in a logic analyzer is disclosed. Each hardware module is connected to a plurality of data channels over which logic signals travel. Each hardware module includes a plurality of hardware event resources configured to determine whether a specified event has occurred; and a plurality of programmable event combiners configured to evaluate a programmed Boolean combination of a plurality of signals generated by a programmed combination of the event resources. The event combiners implement a branch condition statement of a trigger branch in a trigger sequence. The hardware modules also include an occurrence counter that determines whether said branch condition statement evaluates as true a programmed number of occurrences. An action decoder, responsive to the occurrence counter, configure to invoke the event resources to implement one or more actions in an action list of the trigger branch in the trigger sequence. The plurality of event combiners are implemented as RAM look-up tables (LUTs) populated with 1""s and 0""s to implement the programmed Boolean combination of a plurality of programmed LUT inputs.
In one embodiment, the event combiners are interconnected in a logically hierarchical arrangement, and comprise a plurality of pre-combiners and at least one post-combiner. The pre-combiners are connected to a programmed one or more of the event resources to implement a Boolean combination of event result signals generated by the connected event resources. The post-combiner is connected to the pre-combiners to implement a Boolean combination of received pre-combiner result signals, thereby indicating whether the branch condition statement has been evaluated as true of false for a currently-received logic signal.
In a further aspect of the invention a method for translating a branch condition statement of a trigger sequence in a logic analyzer including a plurality of hardware modules is disclosed. The hardware modules are each connected to a plurality of data channels over which logic signals travel. The hardware modules include a plurality of hardware event resources configured to determine whether a specified event has occurred, and a plurality of programmable LUT event combiners configured to evaluate a programmed Boolean combination of a plurality of signals generated by a programmed combination of hardware event resources. The event combiners implement a branch condition statement of a trigger branch in a trigger sequence. The method includes the steps of: (1) expanding the branch condition statement Boolean expression into sum-of-products form; (2) allocating a hardware event resource to implement each event in the branch condition statement; (3) reducing the branch condition statement based on events that always evaluate true or false; (4) expanding the branch condition statement based on pattern or edge events that span multiple hardware modules such that the spanning events are expanded to multiple events that contain only data channels that can be assigned within a single one of the plurality of hardware modules; and (5) populating the combiner LUTs required by each event such that combiners are implemented in a two-level hierarchical scheme with event resources generating values that are provided as inputs to pre-combiners which in turn generate outputs that are provided to a post-combiner.
Various embodiments of the present invention provide certain advantages and overcome certain drawbacks of the conventional techniques. Not all embodiments of the invention share the same advantages and those that do may not share them under all circumstances. Further features and advantages of the present invention as well as the structure and operation of various embodiments of the present invention are described in detail below with reference to the accompanying drawings. In the drawings, like reference numerals indicate identical or functionally similar elements. Additionally, the left-most one or two digits of a reference numeral identifies the drawing in which the reference numeral first appears.